Circuits covered include linear and switching voltage regulators, high speed A/D and D/A data converters, PLLs, comparators, op-amps, and control logic circuits
You will be familiar with ratio-matching, IR drop, and noise coupling as they relate to analog layout
Responsibilities will cover floor planning, physical layout, routing, verification, and final tapeout
Требования
The ideal candidate will be familiar with backend verification tools and will have a good understanding of DRC/LVS/ERC/ANT, extraction of parasitic devices, and integration of digital and analog blocks
Device physics knowledge is a strong plus
The candidate must be able to handle the complexities associated with best layout for lowest cost and maximize silicon area usage
Bachelor degree
5 years or more of Analog layout experience
Analog Design Basics,
Physical verification (DRC, LVS, ERC & DFM)
Proficiency in Layout design environment and EDA tools (Cadence Virtuoso, Mentor Graphics etc.)
Proficiency in debugging layout errors
ESD, Electromigration, Self-heating & IR Drop along with RC Delay, Matching & Decoupling
IC Technology (Fabrication, layout techniques, deep sub-micron effects, Layout design rules)
Design for Manufacturing
Component placement, auto-routing
Routing Techniques: Shielding, Isolation etc
Tapeout and sign-off experience
Power Integrity (power routing to ensure stable & clean power to analog components)
Layout development in multiple technologies & nodes
Scripting (SKILL, Perl, TCL)
Условия
The base annual salary range for this role is between $117,900 - $147,400 USD
