• You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test
• You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle
• As a member of this team you will also be involved in crafting groundbreaking next generation networking chips
• You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities
• Manages the definition, architecture and design of high performance ASICs
• Owns applications or multiple complex functional areas
• Oversees reusable code and its applications
• Creates re-usable code that promotes efficiencies in new ways
• Debugs at system level
• Consults for architecture and design decisions outside of depth areas
• Provides robust design solutions across product
• Re-enforces guidelines/standards across teams
• Defines verification strategies
• Coordinates with appropriate stakeholders to integrate into PD and DV flows
• Owns infrastructure and testing environmens
• Leads and designs the building blocks of multiple channels
• Applies and drives the design methodology from conception to production
• Influences and collaborates with teams to ensure specifications and requirements are met
• Leads technical expertise of a physical design function
• Interfaces with vendors and design leads on full chip timing closure, PI, and PV
• Owns the full electrical planning and specifications of electrical interfaces

Develops multiple solutions, first test vehicles and performs verification and validation

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience
• Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan
• Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators
• Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation

Scripting skills: Tcl, Python/Perl

Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,

• The starting salary range posted for this position is $168,800.00 to $241,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits
• Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training
• The full salary range for certain locations is listed below
• For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance

• Please see the Cisco careers site to discover more benefits and perks
• Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time
• U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies
• Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan

For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota;

• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation
• For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target
• Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid
• For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined

Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements